Field of the Invention
The invention relates to a method for co-designing flip-chips and an interposer, and more particularly to a method for co-designing flip-chips and an interposer to minimize total wire-length and prevent IR violations.
Description of the Related Art
As technology advances, interposer-based three-dimensional integrated circuits (interposer-based 3D ICs, also known as 2.5D ICs) are becoming one of the most promising solutions for enhancing system performance, decreasing power consumption, and supporting heterogeneous integration.
A silicon interposer is not a specific package type, like System in Package (SiP) or Package on Package (PoP). The interposer functions as a larger die to be the carrier of multiple dies. Interposer-based technology is used to connect multiple dies on an interposer and then mount the interposer on a package. In general, the interposer-based technology is a major choice in high-speed applications because of the following advantages: reduced signal lengths, heterogeneous integration, increased process yield against SoC (System on Chip), etc. To enhance these advantages, I/O pads are not only placed along a die boundary (i.e. peripheral-I/O flip-chips), but also in the whole area of the die (i.e. area-I/O flip-chips).
In a conventional design flow, flip-chips are often designed independently, then placed on a silicon interposer, and finally routed with inter-chip connections on the Re-Distribution Layer (RDL) of the interposer. This conventional flow might incur interposer-unfriendly micro bump assignments, and thus requires considerable extra efforts for inter-chip routing, such as IR drops.
Therefore, it is desirable to simultaneously consider a silicon interposer and multiple flip-chips mounted on the silicon interposer.